Charge pumps have been used to generate positive or negative bias voltages for biasing a substrate of an integrated circuit. The output voltage of a charge pump, however, may be used for any application where a voltage above a positive power supply voltage or a voltage below ground potential is necessary in an electrical circuit.
A simple prior art charge pump is shown in FIG. 1. The charge pump of FIG. 1 produces a negative voltage potential at its output for application to, for example, a substrate of an integrated circuit for biasing the substrate. In FIG. 1, clock signal CLK produces a square wave voltage varying between, for example, five volts and ground potential. When a HIGH CLK signal is applied to the upper plate of capacitor C1, an electric field is created across the plates of capacitor C1, and electrons are drawn through diode D1 to charge the bottom plate of capacitor C1 and create a state of equilibrium where the voltage across capacitor C1 is equal to approximately five volts minus the voltage drop across diode D1, or approximately 4.3 volts. At this point in the clock timing sequence, the voltage at node 1 (i.e., at the anode of diode D1) is at ground potential plus the diode drop across diode D1, or approximately 0.7 volts.
As clock signal CLK goes from a HIGH level to ground potential, the existing charge on the bottom plate of capacitor C1 will cause a potential to appear at node 1 equal to approximately 4.3 volts below ground potential, since the voltage across capacitor C1 must remain constant in accordance with the equation: EQU V=Q/C, (eq. 1)
where,
V is the voltage across the capacitor; PA1 Q is the charge on the plates of the capacitor; and PA1 C is the capacitance of the capacitor.
This negative voltage at node 1 forward biases diode D2 and produces a voltage at the output of the charge pump equal to approximately 3.6 volts below ground potential, ignoring any effects of stray capacitance on node 1. Filtering capacitor C.sub.f, coupled to the output of the charge pump, becomes charged to this negative voltage and supplies voltage and current to the load.
Since a typical load consists of a certain amount of resistance, the output voltage of the charge pump diminishes during each clock period due to the charge stored in capacitors C1 and C.sub.f being conducted through the resistive load. This resulting ripple can be decreased somewhat by using a larger capacitor for capacitor C.sub.f.
FIG. 2 shows the level of the clock signal CLK, having a period T, applied to capacitor C1 in FIG. 1. The voltage at node 1 is also shown along with the output of the charge pump, ignoring the effects of any stray capacitance.
When the clock signal CLK goes LOW, the voltage at node 1 becomes negative, and capacitor C1 charges filter capacitor C.sub.f, coupled between the output of the charge pump and ground. As this charge is conducted through the load, the negative output voltage rises toward ground potential until the clock signal again goes LOW to again allow capacitor C1 to charge filter capacitor C.sub.f. As seen in FIG. 2, the ripple of the output voltage has a period equal to the period of the clock signal.
A modification of the charge pump of FIG. 1 is shown in FIG. 3, wherein a relatively high level of negative voltage can be achieved by incorporating additional stages of the charge pump. The operation of the charge pump of FIG. 3 regarding capacitor C1 and diodes D1 and D2 is identical to that described with respect to FIG. 1.
Capacitor C2 of FIG. 3 has its upper plate coupled to clock signal CLK so that when the charge on the bottom plate of capacitor C1 causes a negative potential to appear at node 2 (i.e., the bottom plate of capacitor C2) during a LOW CLK signal, clock signal CLK is at a HIGH value, causing the voltage developed across capacitor C2 to be increased by the negative voltage applied to the bottom plate of capacitor C2. When clock signal CLK then goes LOW, and clock signal CLK goes HIGH, the voltage at node 2 will be made further negative and will be applied to the bottom terminal of capacitor C3 at node 3.
Thus, as seen, the negative voltages at the various nodes becomes more negative toward the output of the charge pump so that the voltage across capacitor C.sub.n may be very high. Accordingly, capacitor C.sub.n must be designed to withstand a greater voltage than the preceding capacitors.
The output of the charge pump of FIG. 3 suffers the same disadvantage as the charge pump of FIG. 1 in that any resistive load coupled to the output of the charge pump of FIG. 3 will cause charge to be dissipated from capacitor C.sub.n and filtering capacitor C.sub.f during the clock cycle, resulting in the ripple of the output voltage having a period equal to the period of the clock signal.
Filter capacitor C.sub.f is needed to help supply voltage and current to the load during the time when clock signal CLK, coupled to the top terminal of capacitor C.sub.n, is HIGH. When CLK goes LOW, capacitor C.sub.f gets recharged by the change on the bottom plate of capacitor C.sub.n.
It would be highly desirable for a circuit designer to use a charge pump having a very low ripple voltage without requiring the charge pump to incorporate capacitors having relatively high capacitance values.